The present invention relates generally to improvements in semiconductor fabrication processes, and more particularly to improvements in processes to improve device scaling.
As well-known in the art, device scaling refers to an amount of semiconductor area required for each active device, such as a transistor, for example. Current semiconductor fabrication processes are limited to the degree to which active devices can be moved closer together. The transistor is a fundamental building block of an integrated circuit.
One popular implementation of the transistor in a semiconductor is formation of a metal-oxide semiconductor (MOS) transistor. This is a common transistor structure, having two active regions, a source and a drain, separated by a channel. A gate controls conductivity of carriers in the channel for conduction or impedance of current between the source and drain.
With current transistor structures, as the channel is shortened and the source and drain are brought closer, the transistor begins to exhibit undesirable characteristics. Some of these undesirable characteristics are instability of a threshold voltage, sub-threshold leakage, current flow when the transistor is to be turned off (I.sub.OFF) and hot carrier injections/degradations. These undesirable characteristics are well-known and will not be further described herein.